The present invention relates to a semiconductor device structure, and more particularly to a semiconductor device structure which can be effectively adapted to bipolar transistors in a very small integrated circuit, which exhibits a very high switching speed, which dissipates very small electric power, and which has a high breakdown voltage.
A conventional representative structure of bipolar transistors is shown in FIG. 1, in which reference numeral 11 denotes a silicon substrate of p conductivity type, and 12a, 12b represent n.sup.+ -type buried layers. The n.sup.+ -type buried layer 12a is connected as a base electrode of a lateral pnp transistor to an electrode 18e via an n.sup.+ -type contact region 13, and the n.sup.+ -type buried layer 12b is connected as a collector electrode of a vertical npn transistor to the electrode 18e via the n.sup.+ -type contact region 13. The lateral pnp transistor is formed by using a p-type region 15a as an emitter, p-type region 15b as a collector, and n-type region 14a as a base. The vertical npn transistor is also formed by using an n.sup.+ -type region 16 as an emitter, p-type region 15c as a base, and n-type region 14b as a collector. Reference numeral 17 denotes an isolation region.
In the device of FIG. 1, parasitic regions unnecessary for the transistor action, i.e., regions under the electrodes 18a, 18b and 18c, occupy more than 80% of the total areas to considerably deteriorate the characteristics of the transistors.
Namely, in the lateral pnp transistor, an excess emitter current and base current flow through an emitter-base junction under the emitter electrode 18a, so that the consumption of electric power increases and the current gain decreases. Further, the hole charge is stored in large amounts in the base region 14a to strikingly deteriorate high-frequency characteristics. In the vertical npn transistor, on the other hand, the capacitance of base-collector junction increases under the base electrode 18c to increase the propagation delay time of the logic circuit. Moreover, when the vertical npn transistor is operated in the reverse direction so that the emitter comes to the substrate side, the region under the base electrode 18c works as a parasitic diode which deteriorates the current gain and high-frequency characteristics. That is, when the vertical npn transistor is operated in the reverse direction, the injection efficiency from the emitter 12b (the collector in the forward operation becomes the emitter in the reverse operation) decreases. Therefore, the presence of these parasitic regions markedly deteriorates the performance of the npn transistors when they are operated in the reverse direction or operated in saturation mode such as in an I.sup.2 L (integrated injection logic) circuit or in a TTL (transistor-transistor logic) circuit.
FIG. 2 shows another conventional bipolar transistor structure which is free from the above-mentioned defects. According to this example, an oxide film 120 is inserted in the parasitic regions to reduce the dissipation of electric power and to gain a high switching speed. In FIG. 2, reference numeral 121 denotes a polycrystalline silicon containing p-type impurities at a high concentration. An emitter region 15a and a collector region 15b of the lateral pnp transistor, as well as a graft base region 15c of the vertical npn transistor, are formed by the diffusion of p-type impurities from the polycrystalline silicon. Reference numeral 19 denotes a p-type intrinsic base region formed by the ion implantation method or the like.
The above-mentioned technique has been disclosed in U.S. Patent Application Nos. 158,366 (June 11, 1980), 435,552 (Oct. 21, 1982) and 527,846 (Aug. 30, 1983).